1. Field of the Invention
The present invention relates to a method whereby the data rate that can be passed through a single radio frequency channel using phase shift or missing cycle modulation can be effectively doubled without increasing the bandwidth of the channel.
2. Description of the Prior Art
“Digital Modulation Device in A System And Method of Using the Same”. U.S. Pat. No. 6,445,737, which issued to the present inventor, and which is incorporated herein by reference, describes a modulation method which transmits a single radio frequency with phase changes at bit period intervals in one to three cycles of the carrier frequency. The modulation is accomplished by either reversing the RF phase for one or more cycles, or by removing one or more cycles from the RF frequency which is transmitted. The method is described as ‘Pulse Position Phase Reversal Keying’ (PPPRM) or (3PRK), or as ‘Missing Cycle Modulation’ (MCM).
The spectrum of these modulation methods is a single frequency line containing more than 95% of the transmitted energy, plus a plurality of sinx/x spectral lines which spread over a wide bandwidth containing less than 5% of the radiated energy. The sinx/x spikes do not contain any useful phase modulation information and can be removed by filtering.
The detector circuit detects the missing cycle, or phase change pulse, or the reversing phase cycle. The detected output is a very narrow pulse one to three RF cycles wide.
The pulses are created in a modulation circuit shown in FIG. 1 that creates a pulse one RF cycle wide at the RF frequency on the rising edge of the data rate clock. This pulse (at time 1) is created only for a digital one. If a digital zero is to be represented, a delay is inserted to cause the zero pulse to occur late (at time 2) with respect to the clock. A decoding circuit utilizes this pulse delay as an indication of a digital one or zero.
In FIG. 1, the pulses for a digital one pass through gates 11 and 12 to the one shot generator 15. The one shot generator 15 creates a pulse having a time duration of one or two RF cycles. This is then applied to a modulator. If phase reversal keying is to be used, the XOR gate 16 is used. If the pulse is to be removed, the AND gate 17 is used. A digital zero passes through gates 13, 14 and 12, to cause a pulse delayed by one bit period plus a small delay amount.
It is not necessary to transmit a pulse representing a zero, since the decoding circuitry (FIG. 2) responds only to the digital ones. A sequence of 10000000100-bits would have a pulse for the 1's, followed by a period of seven bit periods where there would be no alteration in the RF cycles. The decoder recognizes the phase shifts representing the ones, and the RF cycles in which there is no change will be decoded as zeros. The presence of a digital one sets the data clock. If there is a pulse at the start of the data clock, the data is decoded as a one. If there is no pulse the information is read and decoded as a zero.